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MetaMorph CPU

Hardware version of StageCore1. This processor is based on our DLX1-L FPGA micro module and can be integrated into custom hardware. The underlying StageCore1 configuration and firmware can be configured to run the application function.

With application functions usually being implemented on technologically less challenging and more cost-efficient circuit board constructions, the integration of a performat processing system usually scales disproportionate. Our CPU addresses this problem by offloading complexity to a FPGA subprint with own memory and DC-DC converters.

Downloads

Management and Update Tool (NetView) - Java program located inside the zip file.

Firmware Bundle (StageCore1)



Module Pinout


X1FPGA/ModuleX1 X2FPGA/ModuleX2
1C13D62L1_CLRL2_CLR / ISP_CLR1B14B152
3A13C64L1C_CSL2C_CS / ISP_Y3A14B164
5F10B106L1C_DL2C_D / ISP_CS125D11C156
7E11A108ISP_X7D12C168
9B12E1010ISP_CS169D14E1510ISP_ITX
11A12C1012CV_CLK111D16E1612ISP_IRX
13C11C714A1_CSA2_CS13F13F1514
15A11A716A1_DA2_D15F14F1616
G1C_CS17B5D518B1_CSB2_CS17G14H1518G2C_CS
G1CX_D19A5C520B1_DB2_D19G16H1620G2CX_D
G1CY_D21B6F922C1_CSC2_CS21J13J1422G2CY_D
23A6D924C1_DC2_D23K14J1624
25B8E726D1_CSD2_CS25J11K1526
27A8E828D1_DD2_D27J12K1628
CV_CLK229C4F730CV_CLK3ISP_I29L10M1530ISP_R
ISP_U231A4E632ISP_U1ISP_G31M10M1632ISP_B
ISP_U433D8N534ISP_U3MATE_STATUS1_LED33P15N1434
UART_LOG_TX35C8P536ISP_DMX_OUTMATE_STATUS2_LED35P16N1636
UART_MON_TX37C9P438IIC_SCLFEED_STATUS1_LED37R14R1538
UART_MON_RX39A9T440IIC_SDAFEED_STATUS2_LED39T15R1640
READY41M6R542SESSION_LED41L14K1242
43N6T544ISP_DMX_INBRIDGE_LED43L16K1144
45P7P646ERROR_LED45T14G1246
47M7T648RMII_RXD<0>47T13H1148RMII_RX_ER
49L8R750RMII_RXD<1>49R12E1350ETH_PHY_IRQ_N
51L7T752PUSH_BUTTONMII_MDC51T12E1252RMII_TX_EN
53SuspendDone54MII_MDIO53L12H1354RMII_TXD<0>
55GND5V56RMII_CLK55L13H1456RMII_TXD<1>
57GND5V5857M13F1258RMII_CRS_DV
59GND5V60ETH_PEER_LED59P11G1160ETH_PHY_RST_N


Basic core and CPU signals

UART_LOG_TXX1:35Console log (115 kBaud, 8Bit, 1Stop, no parity). StageCore1 uses this UART to send runtime log messages.
UART_MON_RXX1:39User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity)
UART_MON_TXX1:37User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity)

RMII PHY (Micrel KSZ8021RNL or compatible)

RMII_CLKX2:55RMII clock output
RMII_RXD<0>X2:47Receive data input [0]
RMII_RXD<1>X2:49Receive data input [1]
RMII_RX_ERX2:48Receive error input
RMII_CRS_DVX2:58Carrier sense / Receive data valid input
RMII_TXD<0>X2:54Transmit data output [0]
RMII_TXD<1>X2:56Transmit data output [1]
RMII_TX_ENX2:52Transmit enable output
MII_MDCX2:51Management interface (MII) clock output
MII_MDIOX2:53Management interface (MII) data I/O
ETH_PHY_RST_NX2:60PHY reset output, active low, needs external 4k7 pulldown
ETH_PHY_IRQ_NX2:50PHY interrupt input, active low
ETH_PEER_LEDX2:59Peer LED (low = on, Z = off)

System status

READYX1:41System ready condition (everything up and running). Can be used in a condition to open an interlock.
ERROR_LEDX2:45Error LED (red, low = on, Z = off)
SESSION_LEDX2:41Session LED (blue, low = on, Z = off), this LED is controlled by the IDN server and signals an active session.
BRIDGE_LEDX2:43Bridge LED (blue, low = on, Z = off), this LED is controlled by the feed client and signals an active bridge.
MATE_STATUS1_LEDX2:33Mate status LED (green, low = on, Z = off)
MATE_STATUS2_LEDX2:35Mate status LED (green, low = on, Z = off)
FEED_STATUS1_LEDX2:37Feed status LED (green, low = on, Z = off)
FEED_STATUS2_LEDX2:39Feed status LED (green, low = on, Z = off)
PUSH_BUTTONX1:52Push button used for communication/firmware reset and pairing

I²C

A 24C64 type EEPROM (or compatible) shall be reachable at address 0xA8

IIC_SCLX1:38Needs external pullup
IIC_SDAX1:40Needs external pullup

Laser projector: Common converter signals

CV_CLK1X1:12DAC clock output (galvo, laser, color)
CV_CLK2X1:2916 Bit ADC clock output
CV_CLK3X1:3012 Bit ADC clock output

Laser projector: Galvo commands and feedback

Converters used: AD5662xRJ-2 or compatible

G1C_CSX1:17Port 1 galvo chip select output
G1CX_DX1:19Port 1 galvo X output (ISP out: X)
G1CY_DX1:21Port 1 galvo Y output (ISP out: Y)
G2C_CSX2:18Port 2 galvo chip select output
G2CX_DX2:20Port 2 galvo X output (ISP out: U4)
G2CY_DX2:22Port 2 galvo Y output

Laser projector: Laser commands and feedback

The timing of these signals is referenced to the galvo signals (Blankshift). Converters used: DAC7311IDCK or compatible

L1_CLRX1:2Port 1 laser clear output (ISP out: Shutter). This signal indicates the intention of laser emission (low = dark, high = emission).
L1C_CSX1:4Port 1 chip select output
L1C_DX1:6Port 1 data output (ISP out: Intensity)
L2_CLRX2:1Port 2 laser clear output. This signal indicates the intention of laser emission (low = dark, high = emission).
L2C_CSX2:3Port 2 chip select output
L2C_DX2:5Port 2 data output

Laser projector: Color line commands

The timing of these signals is referenced to the laser control signals and can be individually tweaked. Converters used: DAC7311IDCK or compatible

A1_CSX1:14Port 1 line A chip select output
A1_DX1:16Port 1 line A data output (ISP out: R)
B1_CSX1:18Port 1 line B chip select output
B1_DX1:20Port 1 line B data output (ISP out: G)
C1_CSX1:22Port 1 line C chip select output
C1_DX1:24Port 1 line C data output (ISP out: B)
D1_CSX1:26Port 1 line D chip select output
D1_DX1:28Port 1 line D data output
A2_CSX2:13Port 2 line A chip select output
A2_DX2:15Port 2 line A data output (ISP out: U1)
B2_CSX2:17Port 2 line B chip select output
B2_DX2:19Port 2 line B data output (ISP out: U2)
C2_CSX2:21Port 2 line C chip select output
C2_DX2:23Port 2 line C data output (ISP out: U3)
D2_CSX2:25Port 2 line D chip select output
D2_DX2:27Port 2 line D data output

Laser projector: Other signals

ISP_DMX_OUTX1:36DMX512 output according to ISP-DMX standard

Laser projector: ILDA Standard Projector (ISP) input

Converters used: ADS8326(16 Bit) and ADS7866(12 Bit) or compatible

ISP_CS16X2:916 bit converter chip select output
ISP_CS12X2:512 bit converter chip select output
ISP_XX2:7X converter data input (16 Bit)
ISP_YX2:3Y converter data input (16 Bit)
ISP_IX2:29I converter data input (12 Bit)
ISP_RX2:30R converter data input (12 Bit)
ISP_GX2:31G converter data input (12 Bit)
ISP_BX2:32B converter data input (12 Bit)
ISP_U1X1:32U1 converter data input (12 Bit)
ISP_U2X1:31U2 converter data input (12 Bit)
ISP_U3X1:34U3 converter data input (12 Bit)
ISP_U4X1:33U4 converter data input (16 Bit)
ISP_CLRX2:1Shutter input
ISP_ITXX2:10Interlock transmit output
ISP_IRXX2:12Interlock receive output
ISP_DMX_INX1:44DMX512 input according to ISP-DMX standard